Verilog: Is it possible to define array in generate block?
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How can I define an array of "register_bank" in a "generate" block and use them?
I mean something like this:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
register[i][addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= register[i][addr];
end
end
end
endgenerate
verilog
asked Nov 8 at 15:49
M A
341214
add a comment |
up vote
1
down vote
favorite
How can I define an array of "register_bank" in a "generate" block and use them?
I mean something like this:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
register[i][addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= register[i][addr];
end
end
end
endgenerate
verilog
asked Nov 8 at 15:49
M A
341214
add a comment |
up vote
1
down vote
favorite
up vote
1
down vote
favorite
How can I define an array of "register_bank" in a "generate" block and use them?
I mean something like this:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
register[i][addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= register[i][addr];
end
end
end
endgenerate
verilog
asked Nov 8 at 15:49
M A
341214
How can I define an array of "register_bank" in a "generate" block and use them?
I mean something like this:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
register[i][addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= register[i][addr];
end
end
end
endgenerate
verilog
verilog
asked Nov 8 at 15:49
M A
341214
asked Nov 8 at 15:49
M A
341214
edited Nov 8 at 17:16
asked Nov 8 at 15:49
M A
341214
asked Nov 8 at 15:49
M A
341214
asked Nov 8 at 15:49
M A
341214
341214
add a comment |
add a comment |
1 Answer
1
active
oldest
votes
up vote
0
down vote
I just found the answer. We can do that using the name of the block. Just like the following code:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being : my_reg_bank
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
my_reg_bank[i].register[addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= my_reg_bank[i].register[addr];
end
end
end
endgenerate
answered Nov 8 at 17:15
M A
341214
add a comment |
1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
0
down vote
I just found the answer. We can do that using the name of the block. Just like the following code:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being : my_reg_bank
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
my_reg_bank[i].register[addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= my_reg_bank[i].register[addr];
end
end
end
endgenerate
answered Nov 8 at 17:15
M A
341214
add a comment |
up vote
0
down vote
I just found the answer. We can do that using the name of the block. Just like the following code:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being : my_reg_bank
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
my_reg_bank[i].register[addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= my_reg_bank[i].register[addr];
end
end
end
endgenerate
answered Nov 8 at 17:15
M A
341214
add a comment |
up vote
0
down vote
up vote
0
down vote
I just found the answer. We can do that using the name of the block. Just like the following code:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being : my_reg_bank
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
my_reg_bank[i].register[addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= my_reg_bank[i].register[addr];
end
end
end
endgenerate
answered Nov 8 at 17:15
M A
341214
I just found the answer. We can do that using the name of the block. Just like the following code:
genvar i;
generate
for(i = 0; i < 4; i = i + 1)
being : my_reg_bank
reg [15:0] register_bank [0:31];
always @(posedge clk)
begin
if(we)
begin
my_reg_bank[i].register[addr] <= data_i[i * 16 +: 16];
end
else
begin
data_o[i * 16 +: 16] <= my_reg_bank[i].register[addr];
end
end
end
endgenerate
answered Nov 8 at 17:15
M A
341214
answered Nov 8 at 17:15
M A
341214
answered Nov 8 at 17:15
M A
341214
answered Nov 8 at 17:15
M A
341214
341214
add a comment |
add a comment |
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